`timescale 1ns / 1ps

module timer(Clock_i,Clock_OneSecond_i,start_timer_i,value_i,timeOut,expired_o);
 
input Clock_i,Clock_OneSecond_i,start_timer_i;
input [3:0] value_i;
output reg expired_o = 1;
output reg [3:0] timeOut;
reg [3:0]counter=4'd1;

 
always @( posedge Clock_i)
	begin
		if(start_timer_i)//
			begin
			expired_o <= 1;
			timeOut <= 4'd0; 
			counter <=4'd1; 
			end
		else
			begin		
			if (Clock_OneSecond_i)
				begin	
					if(counter == value_i)
							begin
								counter <=4'd1;								
								timeOut <= value_i - counter;
								expired_o <= 0;
							end
						else
							begin
								expired_o <= 1;
								counter <= counter + 1;
								timeOut<=value_i-counter;
							end									
				end
				else begin expired_o <= 1; counter <= counter; timeOut<=timeOut; end
			end
	end


endmodule
